PLLs are commonly used in radio frequency (RF) applications, such as in wireless modems. In these types of applications, it is important that the PLL be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Some examples of conventional circuits are: U.S. patent application Ser. No. 12/726,190, Wu et al., “A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop,” IEEE 2007 Custom Intergrated Circuits Conference, pp. 547-550; Nonis et al., “Modeling, Design and Characterization of a New Low-Jitter Analog Dual Tuning LC-VCO PLL Architecture,” IEEE J. OF Solid-State Circuits, Vol. 40, No. 6, June 2005, pp. 1303-1309; Perrott et al., “A 2.5-Gb/s Multi-Rate 0.25-m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition,” IEEE J. OF Solid-State Circuits, Vol. 41, No. 12, December 2006, pp. 2930-2944; U.S. Pat. No. 6,658,748; U.S. Pat. No. 6,952,124; U.S. Pat. No. 7,015,763; U.S. Pat. No. 7,133,485; U.S. Pat. No. 7,301,407; U.S. Pat. No. 7,385,452; U.S. Pat. No. 5,909,149; U.S. Pat. No. 5,942,949; U.S. Pat. No. 6,323,736; U.S. Pat. No. 6,661,267; U.S. Pat. No. 6,731,712; U.S. Pat. No. 7,047,146; U.S. Pat. No. 7,154,346; U.S. Pat. No. 7,177,382; U.S. Pat. No. 7,532,696; U.S. Pat. No. 7,684,763; U.S. Patent Pre-Grant Publ. No. 2002/0008593; U.S. Patent Pre-Grant Publ. No. 2003/0141936; U.S. Patent Pre-Grant Publ. No. 2005/0212609; U.S. Patent Pre-Grant Publ. No. 2005/0212614; U.S. Patent Pre-Grant Publ. No. 2007/0057736; U.S. Patent Pre-Grant Publ. No. 2003/0206042; U.S. Patent Pre-Grant Publ. No. 2004/0164812; U.S. Patent Pre-Grant Publ. No. 2005/0137816; datasheet for Texas Instruments Incorporated's CDCE421; datasheet for Analog Device Inc.'s ADF4350; and European Patent Appl. No. EP1256170.
Therefore, there is a need for an improved PLL.